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Lattice ECP3
LatticeECP3 Family - Lowest Power. Highest Value. Innovative. In
Production.
The LatticeECP3 family, is the third generation high value FPGA from Lattice
Semiconductor, which offers the industry’s lowest power consumption and price of
any SERDES-capable FPGA device. The LatticeECP3 FPGA family offers
multi-protocol 3.2G SERDES with XAUI jitter compliance, DDR3 memory interfaces,
powerful DSP capabilities, high density on-chip memory and up to 149K LUTS, all
with half the power consumption and half the price of competitive SERDES-capable
FPGAs. The entire LatticeECP3 family is manufactured using Fujitsu’s advanced
low power 65nm process technology.
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Key Features
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- Lowest-Power FPGA with SERDES
- Low Power 65-nm process
- Up to 80% lower static power, and 50% lower total power relative to the
competition
- Less than 100mW per SERDES channel @ 3.2 Gbps
- Optimized FPGA Architecture
- 4-input look-up table (LUT) fabric
- Logic densities from 17K to 149K LUTs
- Up to 6.8Mbits of Embedded Block RAM (EBR)
- 2 DLLs per device, 2 to 10 PLLs per device
- Cascadable sysDSP™ With ALU
- Multiply, accumulate, addition and subtraction
- High performance Adder Trees and MMAC functionality
- 54-bit cascadable arithmetic logic unit
- 24 to 320 multipliers (18x18)
- Advanced Configuration Options
- Parallel burst mode for SPI Flash
- Automatic multi-boot capability
- On chip 128 bit AES decryption
- Live update with TransFR™ Technology
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- High Speed Embedded SERDES
- Up to 16 channels @ 3.2Gbps
- Data rates from 250Mbps to 3.2Gbps
- IEEE802.3-2002 XAUI Jitter Compliant
- Mixed Protocol and Mixed Rate support
- Supports PCI Express, Ethernet (GbE, XAUI, & SGMII), SMPTE, Serial Rapid
I/O, CPRI and OBSAI
- Flexible sysIO™ Buffers
- LVCMOS 33/25/18/15/12, PCI, SSTL3/2/18 & HSTL15 & HSTL18
- LVDS, Bus-LVDS, MLVDS & LVPECL
- 800 Mbps DDR3, 1 Gbps LVDS
- Wide Range of Package and User I/O Options
- Up to 586 user I/O pins
- Low cost wirebond fpBGA packages
- Pb-free / RoHS-compliant
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Evaluation Boards
In order to accelerate your design development, Lattice offers a choice of
development boards to support LatticeECP3 designs. The development boards enable
you to evaluate the benefits of the LatticeECP3 devices capabilities in a lab
setting.
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The LatticeECP3 Serial Protocols board provides a platform
to evaluate
- DDR2 memory interface
- PCI express
- Gigabit ethernet
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The LatticeECP3 I/O Protocols board provides a platform to
evaluate
- DDR3 memory interface
- SPI4.2
- ADC/DAC interfaces
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The LatticeECP3 Video board provides a platform to evaluate
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Design Solutions
- Wireless Solutions
- Video Broadcast Solutions
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- PCI Express Solutions
- Ethernet Solutions
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Device Selection Guide
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Device
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ECP3-17
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ECP3-35
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ECP3-70
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ECP3-95
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ECP3-150
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LUTs (K)
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17
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33
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67
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92
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149
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EBR SRAM (Kbits)
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552
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1327
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4420
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4420
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6850
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EBR SRAM Blocks
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30
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72
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240
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240
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372
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Distributed RAM (Kbits)
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36
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68
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145
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188
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303
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18x18 Multipliers
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24
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64
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128
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128
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320
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3.2Gbps SERDES Channals
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4
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4
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12
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12
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16
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Maximum Available I/O
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222
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310
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490
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490
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586
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PLLs + DLLs
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2+2
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4+2
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10+2
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10+2
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10+2
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Packages
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SERDES I/O Combinations
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256-ball ftBGA (17 x 17 mm)
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4 / 133
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4 / 133
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| 484-ball fpBGA (23 x 23 mm) |
4 / 222
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4 / 295
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4 / 295
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4 / 295
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| 672-ball fpBGA (27 x 27 mm) | |
4 / 310
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8 / 380
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8 / 380
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8 / 380
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| 1156-ball fpBGA (35 x 35 mm) | | |
12 / 490
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12 / 490
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16 / 586
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Contacts
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