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Lattice ECP3


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LatticeECP3 Family - Lowest Power.  Highest Value.  Innovative.  In Production.

The LatticeECP3 family, is the third generation high value FPGA from Lattice Semiconductor, which offers the industry’s lowest power consumption and price of any SERDES-capable FPGA device. The LatticeECP3 FPGA family offers multi-protocol 3.2G SERDES with XAUI jitter compliance, DDR3 memory interfaces, powerful DSP capabilities, high density on-chip memory and up to 149K LUTS, all with half the power consumption and half the price of competitive SERDES-capable FPGAs. The entire LatticeECP3 family is manufactured using Fujitsu’s advanced low power 65nm process technology.

Key Features

  • Lowest-Power FPGA with SERDES
    • Low Power 65-nm process
    • Up to 80% lower static power, and 50% lower total power relative to the competition
    • Less than 100mW per SERDES channel @ 3.2 Gbps
  • Optimized FPGA Architecture
    • 4-input look-up table (LUT) fabric
    • Logic densities from 17K to 149K LUTs
    • Up to 6.8Mbits of Embedded Block RAM (EBR)
    • 2 DLLs per device, 2 to 10 PLLs per device
  • Cascadable sysDSP™ With ALU
    • Multiply, accumulate, addition and subtraction
    • High performance Adder Trees and MMAC functionality
    • 54-bit cascadable arithmetic logic unit
    • 24 to 320 multipliers (18x18)
  • Advanced Configuration Options
    • Parallel burst mode for SPI Flash
    • Automatic multi-boot capability
    • On chip 128 bit AES decryption
    • Live update with TransFR™ Technology
  • High Speed Embedded SERDES
    • Up to 16 channels @ 3.2Gbps
    • Data rates from 250Mbps to 3.2Gbps
    • IEEE802.3-2002 XAUI Jitter Compliant
    • Mixed Protocol and Mixed Rate support
    • Supports PCI Express, Ethernet (GbE, XAUI, & SGMII), SMPTE, Serial Rapid I/O, CPRI and OBSAI
  • Flexible sysIO™ Buffers
    • LVCMOS 33/25/18/15/12, PCI, SSTL3/2/18 & HSTL15 & HSTL18
    • LVDS, Bus-LVDS, MLVDS & LVPECL
    • 800 Mbps DDR3, 1 Gbps LVDS
  • Wide Range of Package and User I/O Options
    • Up to 586 user I/O pins
    • Low cost wirebond fpBGA packages
    • Pb-free / RoHS-compliant

Evaluation Boards

In order to accelerate your design development, Lattice offers a choice of development boards to support LatticeECP3 designs. The development boards enable you to evaluate the benefits of the LatticeECP3 devices capabilities in a lab setting.

The LatticeECP3 Serial Protocols board provides a platform to evaluate

  • DDR2 memory interface
  • PCI express
  • Gigabit ethernet

LatticeECP3 board

The LatticeECP3 I/O Protocols board provides a platform to evaluate

  • DDR3 memory interface
  • SPI4.2
  • ADC/DAC interfaces

Lattice ECP3 IO

The LatticeECP3 Video board provides a platform to evaluate

  • SMPTE
  • 7:1 LVDS

Lattice ECP3 Video

Design Solutions

  • Wireless Solutions
  • Video Broadcast Solutions
  • PCI Express Solutions
  • Ethernet Solutions

Device Selection Guide

Device

ECP3-17

ECP3-35

ECP3-70

ECP3-95

ECP3-150

LUTs (K)

17

33

67

92

149

EBR SRAM (Kbits)

552

1327

4420

4420

6850

EBR SRAM Blocks

30

72

240

240

372

Distributed RAM (Kbits)

36

68

145

188

303

18x18 Multipliers

24

64

128

128

320

3.2Gbps SERDES Channals

4

4

12

12

16

Maximum Available I/O

222

310

490

490

586

PLLs + DLLs

2+2

4+2

10+2

10+2

10+2

Packages

SERDES I/O Combinations

256-ball ftBGA (17 x 17 mm)

4 / 133

4 / 133

484-ball fpBGA (23 x 23 mm)

4 / 222

4 / 295

4 / 295

4 / 295

672-ball fpBGA (27 x 27 mm)

4 / 310

8 / 380

8 / 380

8 / 380

1156-ball fpBGA (35 x 35 mm)

12 / 490

12 / 490

16 / 586

Contacts

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Lattice ECP3