Low Power SRAM Roadmap

While the sales of low capacity SRAM (256-Kbit to 1-Mbit) are showing a stable demand situation, models with a capacity of 4-Mbit to 16-Mbit are in the volume zone. Furthermore, the need for models with a high capacity of 16-Mbit and 32-Mbit has been increasing recently. Renasas has been mass-producing a 16-Mbit and a 32-Mbit (16-Mbit x 2 chips) Advanced LPSRAM. For the next step the number of models with both higher and lower capacities will be increased. The next device that has been released under this strategy is a 4-Mbit chip with an operation power of 3.3V produced in 0.15μm. Furthermore Renesas is going to introduce the 32-Mbit single chip models and the 64-Mbit models (32-Mbit two chips) into the market within 2008.

The three categories of Renesas SRAM strategy

Advantages of Advanced Low Power SRAM

Circuit structure

The Advanced LPSRAM is based on two technologies – TFT load and DRAM capacitors (Diagram). The TFT technology enables the use of polysilicon TFTs as load transistors that load the flip-flop circuit.

Use of polysilicon TFTs achieves miniaturization but with the Advanced LPSRAM, the cell size was reduced by two transistors out of six by stacking the TFTs.

Furthermore, stacking TFTs enabled the use of N channel transistors (load transistors and access transistors) only, which eliminated the risk of the latch-up effect caused by parasitic transistors. At the same time, gaps to prevent the latch-up effect are no longer necessary, leading to further miniaturization and improved reliability. The second idea is to drastically increase the accumulated charge amount by adding capacitors on the circuit. For Advanced LPSRAM, this signifi - cantly improved the resistance to software errors.

Package Line-up

One nice feature of Renesas low-power SRAM is their full package line-up. Naturally, packages are becoming smaller – for instance, for the lead type, a 52-pin μTSOP (body dimension: 10.49mm x 10.79mm x 1.2mm) can be used for 8-Mbit/16-Mbit/ 32-Mbit SRAM. For 52-pin products the pinout can remain the same even when the memory capacity is increased, therefore the board layout does not have to be changed.

On the other hand, for the non-lead type, Renesas has been supplying products in FBGA packages and now also wafer sized CSP package products are available.
There are two types of capacity supplied in these packages – 4-Mbit and 16-Mbit. 4-Mbit is supplied in 3.55mm x 4.45mm packages and 16-Mbit in 5.62mm x 5.28mm packages.

These packages are much smaller, with the mounting areas reduced by 75% (4-Mbit) and 49% (4-Mbit) compared to conventional FBGA packages. Also they have become thinner to 0.74mm (4-Mbit) and 0.79mm (16-Mbit).

Comparison between Wafer Level CSPs and FBGA

Preventing SRAM Software Errors

In SRAM, the memory status occasionally is reversed even though the hardware is working properly. There is no trace of this event in the memory itself, which is different from hardware defects and failures. This is called “Software error”. There are two causes of software errors. Some errors are caused by alpha-particles. When alphaparticles generated from radioactive impurities enter the silicon, electrical charges are released. These charges are collected in the memory node, which causes the data to reverse. The effects of this event can be reduced to a certain extent by carefully choosing materials such as mould resin. Another cause is neutron rays from space. Some neutrons that entered the chip collide with nuclei in the silicon and if charged particles are generated, the nuclei in the silicon move to generate electrical charges. Neutron rays exist everywhere on Earth and even go through shields, etc., so it is diffi cult to solve this cause. Therefore, 16-Mbit LPSRAM have an error correction circuit (ECC) to automatically correct any errors, while Advanced LPSRAM use a DRAM capacitor, which controls the fl uctuation of the electrical charges and software errors can be ignored.